1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly it relates to a non-volatile semiconductor memory device which is rewritable block by block.
2. Description of the Related Arts
Hitherto, a variety of memories have been proposed as flash memories capable of rewriting data block by block. As an example thereof, operation of an NOR-type memory having a floating gate using an FN writing/FN erasing cell will be described hereinafter with reference to FIG. 3.
In a writing operation, a source is let open and a voltage of 0V is applied to a substrate (P-well), -9V to a control gate and 5V to a drain to extract electrons from the floating gate into the drain, thereby to decrease a threshold voltage Vth of the memory cell.
In an erasing operation, the drain is let open and a voltage of -8V is applied to the source and the substrate (P-well) and 10V to the control gate to inject electrons from the channel into the floating gate, thereby to increase the threshold voltage Vth of the memory cell.
In a reading operation, a voltage of 1V is applied to the drain, 0V to the source and the substrate (P-well) and 3V to the control gate to determine whether or not a current flows in the memory cell, thereby to detect whether or not the writing has been performed (i.e. whether the written data is "0" or "1") in the memory cell.
Referring to FIG. 3, a plurality of memory cells which operate as mentioned above are arranged in a row direction and in a column direction to form a memory array in which the control gate is connected to a word-line and the drain is connected to a bit-line.
In a flash memory, generally, the whole memory array is erased collectively. However, because the whole tip is too large as a unit for erasure, one tip is divided into a plurality of blocks so as to allow erasure of the data block by block.
In such memories, writing operation is generally performed simultaneously on cells connected to one word-line within a block and this writing operation is performed for every word-line.
Accordingly, each block in the memory is independently subjected to the erasing/writing operation, so that rewriting of 10.sup.4 to 10.sup.5 times must be ensured in each block in order to ensure rewriting of 10.sup.4 to 10.sup.5 times in the whole tip.
In the case where the erasing/writing operation is independently performed in each block, it is necessary to consider the effect (disturbance) which the erasing/writing operation of one block gives to the data in another block. In the above-mentioned cell operation, the following two modes appear as disturbances to be considered in writing.
The first mode is a mode called "drain disturb". In writing, a voltage of 5V is applied to a selected bit-line (drain), so that cells on the same bit-line are stressed by this voltage even if the cells are not subjected to the writing operation. This stress causes electrons to escape from the floating gate into the drain and thus, Vth of such cells drops slightly as compared with the cell which is subjected to the writing operation. The stress described above is very small compared with a stress caused by the writing operation. However, the effect generated by the stress cannot be ignored if the cells continue to receive the stress for a long time. In the above example, when Vth of the cell having a data of high Vth drops lower than a prescribed voltage of 3V, the cell will be a fail bit.
The writing operation is performed as many times as the number of the word-lines. Therefore, in the writing operation for one block, the cells are disturbed for a period of time of (the period of time for writing data into one cell).times.(the number of word-lines in the block). Further, if one bit-line is shared by a plurality of blocks, cells of a block which has not been selected for writing receive this disturbance as well. For example, assuming that the number of rewriting times is 10.sup.5, the number of word-lines in one block is 10.sup.3 and the bit-line is shared by four blocks, then the possible period of time of drain disturbance for one block is 10.sup.3.times. 4.times.10.sup.5 times as long as the period of time for writing one cell.
The second mode is a mode called "gate disturb". At the time of writing, a voltage of -9V is applied to a selected word-line (control gate), so that the cells on the same word-line are stressed by this voltage even if the cells are not subjected to the writing operation. This stress causes electrons to escape from the floating gate into the substrate (P-well) and thus, Vth of such cells drops slightly as compared with the cell which is subjected to the writing operation. In the above example, when Vth of the cell having a data of high Vth drops lower than a prescribed voltage of 3V, the cell will be a fail bit.
If one word-line is shared by a plurality of blocks, cells of a block which has not been selected for writing receive this gate disturbance as well. For example, assuming that the number of rewriting times for one block is 10.sup.5 and a word-line is shared by four blocks, then the possible period of time of gate disturbance for one block is 4.times.10.sup.5 times as long as the period of time for writing data into cells on the word-line of one block.
As a countermeasure against such disturbance, a conventional memory cell has been provided with a decoding circuit for each block so as to make a bit-line and a word-line of each block independent, as shown in FIG. 4. Alternatively, a main bit-line/sub bit-line structure and a main word-line/sub word-line structure have been adopted using a local decoder (or a selection transistor), as shown in FIG. 5, so that a high voltage of writing/erasing will not be applied to the sub bit-line or the sub word-line of a non-selected block even if the high voltage of writing/erasing is applied to the main bit-line or the main word-line.
However, if the above-mentioned structure shown in FIG. 4 is adopted, there arises a problem that an area of a tip increases because every block is provided with a decoding circuit. On the other hand, if a main bit-line/sub bit-line structure and a main word-line/sub word-line structure shown in FIG. 5 are adopted, it is necessary to wire a memory cell with two lines, i.e. a main line and a sub line, so that there arises a problem that the number of wiring layers and thus the number of production steps increase, leading to increased production costs and low yield.
On the other hand, Japanese Unexamined Patent Publication No. HEI 8(1996)-195090 proposes a non-volatile semiconductor memory device provided with a voltage converter for each block so as to apply a first voltage, which is required for writing, to a word-line of a block selected among a plurality of blocks for writing and to apply a second voltage, which has a smaller absolute value than the first voltage, to a word line of the other blocks in performing the writing operation. This provides a method in which the writing operation is performed using the first voltage and the selection of the word line is communicated (transmitted) to other blocks using the first or second voltage.
However, although the gate disturb can be avoided by this method, it is not possible to avoid the drain disturb. Moreover, even if an attempt is made to apply a method similar to this as a countermeasure against the drain disturb, there arises a problem that it is not possible to connect each cell directly to a sensing amplifier in a reading operation because each cell is connected to the bit-line decoder through a voltage conversion circuit, so that this method cannot be directly applied for avoiding the drain disturb. Further, since this method presupposes a writing operation using hot electrons, there arises a problem that a large electric current driving capability is required in the voltage conversion circuit which is provided in each block, thereby increasing the area of the circuit.